In a charged particle beam exposure apparatus, for example, an electron beam exposure apparatus, when preparing circuit patterns (element formation patterns) of a large scale integrated circuit etc., a high level of processing capability per unit time (throughput) is required.
An electron beam exposure apparatus answering such a demand is disclosed in for example Japanese Unexamined Patent Publication (Kokai) No. 5-160012 and Japanese Patent No. 2951947.
FIG. 1 is a schematic view of an example of an electron beam exposure apparatus of a type similar to that disclosed in the above publications. This electron beam exposure apparatus 10 is configured as a so-called LEEPL type designed to make a wafer or other specimen (exposed body) moved at suitable times by operation of a table in a state with a stencil mask 20 fixed. In the description of the present application, “stencil mask” refers to a mask having opening areas with no substances present in the spaces.
As shown in FIG. 1, the electron beam exposure apparatus 10 is provided with an electron beam source 12 for emitting an electron beam Eb, a focusing optical system 14 for focusing the electron beam Eb, a main deflector 16 for deflecting the electron beam Eb focused by the focusing optical system 14, and a fine adjustment deflector 18 and projects the electron beam Eb passed through the fine adjustment deflector 18 via the stencil mask 20 to the surface of the specimen 21.
The electron beam exposure apparatus 10 is provided with a mask stage for holding the stencil mask 20 and the table for holding a specimen 21 at a location where the circuit patterns (opening patterns) are projected by the electron beam Eb passed through the stencil mask 20.
In the electron beam exposure apparatus 10 having the above configuration, the exposure is started in a state where the stencil mask 20 is mounted on the mask stage and then a specimen 21 having a resist film (not illustrated) coated on the surface is placed on the table.
At this time, when the electron beam Eb is emitted from the electron beam source 12, the electron beam Eb passed through the focusing optical system 14, main deflector 16, and fine adjustment deflector 18 passes through the circuit patterns of the stencil mask 20, then is exposed by projection onto the resist film at the surface of the specimen 21 as the circuit patterns.
In the electron beam exposure apparatus 10, however, the electron beam Eb used for the projection of the circuit patterns has a nature whereby energy is absorbed even when passing through a transparent substance for visible light or ultraviolet ray, so the stencil mask 20 cannot be configured by transparent, strong silica glass or the like. For this reason, in order to make the electron beam Eb pass well at the time of projection exposure, there is no method other than the method of forming the circuit patterns by openings.
In this way, the stencil mask 20 is a self-supporting type transmission mask where circuit patterns of regions passing the electron beam are all formed by openings, therefore cannot be provided with donut-shaped patterns where peripheries are all surrounded by openings. Accordingly, it is impossible to expose by projection donut-shaped patterns onto a specimen 21 by merely using one such stencil mask 20.
In order to solve the problem of the above donut-shaped patterns, the complementary mask division method for dividing one circuit pattern among a plurality of complementary stencil masks is disclosed in for example Japanese Examined Patent Publication (Kokoku) No. 7-66182.
In the complementary mask division method disclosed in this publication, the relatively simple layout of a semiconductor chip is divided into a plurality of sections, and the divided sections are assigned to two complementary stencil masks. Further, these two complementary stencil masks are used to sequentially expose sections of the layout formed at the complementary stencil masks onto the surface of the specimen (exposed body) and thereby transfer the entire circuit patterns.
In the description of the present application, “complementary masks” mean masks dividing patterns of a certain section and placing the parts on a plurality of masks or placing them on different areas of the same mask and able to form the patterns of that section as before division by overlaying the masks or different areas of the same mask to overlay the divided parts of the patterns.
Also, in the description of the present application, “complementary stencil masks” mean stencil masks dividing patterns of a certain section and placing the parts on a plurality of stencil masks or placing them on different areas of the same stencil mask and able to form the patterns of that section as before division by overlaying the stencil masks or different areas of the same stencil mask to overlay the divided parts of the patterns.
In the field of production of semiconductor integrated circuits in recent years, in response to the demand for further larger integration, there has been a trend toward an increase of the number of devices configuring the semiconductor integrated circuits and greater miniaturization of each device. Due to this, the circuit patterns comprised by the openings for exposing by projection the patterns of the devices onto the specimen by an irradiated electron beam are becoming more miniaturized.
Accordingly, the pattern density of the openings forming circuit patterns has increased. With the complementary stencil masks used in the above conventional complementary mask division method or the like, the mechanical strength falls, distortion or other deformation becomes easy to occur in the circuit patterns, and even breakage occurs in remarkable cases.
When distortion or other deformation occurs in complementary stencil masks, overlay accuracy no longer can be carried out between the specimen and the complementary stencil masks. Also, the electron beam passed through the distorted circuit patterns is exposed by projection onto the specimen, so the accurate circuit patterns cannot be transferred.